CXD3406GA

Timing Generator and Signal Processor for Frame Readout CCD Image Sensor

Description

The CXD3406GA is a timing generator and CCD

signal processor IC for the ICX252/262 CCD image

sensor.

Features

· Timing generator functions

· Horizontal drive frequency 12 to 18MHz

(Base oscillation frequency 24 to 36MHz)

· Supports frame readout/draft (sextuple speed)/

AF (Auto focus drive)

· High-speed/low-speed shutter function

· Horizontal and vertical drivers for CCD image

sensor

· CCD signal processor functions

· Correlated double sampling

· Programmable gain amplifier (PGA) allows gain

adjustment over a wide range (6 to +42dB)

· 10-bit A/D converter

· Chip Scale Package (CSP):

CSP allows vast reduction in the CCD camera

block footprint

Applications

Digital still cameras

Structure

Silicon gate CMOS IC

Applicable CCD Image Sensors

ICX252 (1/1.8", 3240K pixels)

ICX262 (1/1.8", 3240K pixels)

Absolute Maximum Ratings

· Supply voltage

a, V

b, V

c, V

0.3 to +7.0

e, V

f, V

0.3 to +4.0

10.0 to V

VL 0.3 to +26.0

· Input voltage (analog)

0.3 to V

+ 0.3

· Input voltage (digital)

0.3 to V

+ 0.3

· Output voltage

0.3 to V

+ 0.3

VL 0.3 to V

+ 0.3

VL 0.3 to VH + 0.3

· Operating temperature

Topr

20 to +75

°C

· Storage temperature

Tstg

55 to +125

°C

Recommended Operating Conditions

· Supply voltage

3.0 to 5.5

a, V

c, V

3.0 to 3.6

0.0

14.5 to 15.5

7.0 to 8.0

e, V

f, V

3.0 to 3.6

· Operating temperature

Topr

20 to +75

°C

E00Z02A26

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

96 pin LFLGA (Plastic)

CXD3406GA

Block Diagram

DD3

DD4

SS3

SS4

SS5

SCK2

SSI2

SEN2

TEST3

TEST4

TEST5

DD1

SS3

DD2

SS1

SS2

D0 (LSB)

Latch

Serial Port

DAC

PGA

CDS

ADC

Preblanking

Dummy Pixel

Auto Zero

Pulse Generator

V Driver

Serial Port

Black Level

Auto Zero

D9 (MSB)

ADCLKI

CLPOBI

CLPDMI

SS4

ADCLK

CLPOB

CLPDM

SS5

OSCI

OSCO

CKI

CKO

MCKO

SNCSL

SSI1

WEN

SS3

DD3

SS2

DD2

DD4

XRS

PBLK

XSHD

XSHP

PBLKI

XSHDI

SS2

XSHPI

SS1

DD2

DD1

CCDIN

SS6

DD5

SCK1

SEN1

SS6

SS1

DD5

DD1

SUB

V3B

V3A

V1B

TEST2

TEST1

RST

SSG

SSGSL

V1A

Latch

Selector

1/2

CXD3406GA

Pin Configuration (Top View)

SS2

ADCLKI

ADCLK

CKI

OSCO

OSCI

SCK1

SEN1

DD1

SS3

CLPOBI

CLPOB

CKO

MCKO

SSI1

SCK2

SS1

DD2

CLPDMI

CLPDM

SS5

DD5

SS4

TEST1

SS6

SSI2

SEN2

TEST4

TEST3

TEST5

SS5

V1A

V1B

SS4

DD4

V3A

V3B

SS2

PBLKI

PBLK

XRS

SS3

DD2

SS1

TEST2

SUB

SS6

DD3

DD2

XSHDI

XSHD

DD4

SSGSL

RST

SNCSL

DD5

SS3

CCDIN

DD1

XSHPI

XSHP

DD3

SS2

DD1

WEN

CXD3406GA

Pin Description

No connected.

CCD signal processor block serial interface clock input. (Schmitt trigger)

CCD signal processor block serial interface data input. (Schmitt trigger)

CCD signal processor block test input 3. Connect to DV

CCD signal processor block analog GND.

Capacitor connection.

CCD signal processor block analog GND.

CCD signal processor block analog power supply.

ADC output.

ADC output (LSB).

CCD signal processor block serial interface enable input. (Schmitt trigger)

CCD signal processor block test input 5. Connect to DV

CCD signal processor block analog power supply.

Capacitor connection.

CCD signal processor block analog power supply.

CCD signal processor block analog GND.

ADC output.

CCD signal processor block test input 4. Connect to DV

CCD signal processor block analog GND.

Capacitor connection.

CCD output signal input.

ADC output.

Capacitor connection.

CCD signal processor block analog GND.

ADC output (MSB).

CCD signal processor block digital power supply. (Power supply for ADC)

SCK2

SSI2

TEST3

SS4

SS6

DD5

SEN2

TEST5

DD4

DD3

SS3

TEST4

SS5

CCDIN

SS1

DD1

No.

Symbol

I/O

Description

CXD3406GA

CCD signal processor block digital GND. (GND for ADC)

CCD signal processor block analog GND.

CCD signal processor block analog power supply.

CCD signal processor block digital GND.

CCD signal processor block digital power supply.

Pulse input for horizontal and vertical blanking period pulse cleaning. (Schmitt trigger)

CCD data level sample-and-hold pulse input. (Schmitt trigger)

CCD precharge level sample-and-hold pulse input. (Schmitt trigger)

Clock input for analog/digital conversion. (Schmitt trigger)

CCD optical black signal clamp pulse input. (Schmitt trigger)

CCD dummy signal clamp pulse input. (Schmitt trigger)

Pulse output for horizontal and vertical blanking period pulse cleaning.

CCD data level sample-and-hold pulse output.

CCD precharge level sample-and-hold pulse output.

Clock output for analog/digital conversion.

CCD optical black signal clamp pulse output.

CCD dummy signal clamp pulse output.

Sample-and-hold pulse output for analog/digital conversion phase alignment.

Timing generator block digital power supply. (Power supply for CDS block)

Timing generator block 3.0 to 5.0V power supply. (Power supply for H1/H2)

Inverter input.

Inverter output.

Timing generator block digital GND.

CCD horizontal register clock output.

Inverter output for oscillation. When not used, leave open or connect a capacitor.

System clock output for signal processor IC.

Timing generator block digital power supply. (Power supply for common logic block)

Timing generator block digital power supply. (Power supply for RG)

CCD reset gate pulse output.

Timing generator block digital GND.

Inverter input for oscillation. When not used, fix to low.

SS1

SS2

DD2

DD1

SS2

SS3

DD2

PBLKI

XSHDI

XSHPI

ADCLKI

CLPOBI

CLPDMI

PBLK

XSHD

XSHP

ADCLK

CLPOB

CLPDM

XRS

DD4

DD3

CKI

CKO

SS5

SS3

OSCO

MCKO

DD5

DD2

SS2

OSCI

No.

Symbol

I/O

Description

CXD3406GA

Timing generator block serial interface data input.
Schmitt trigger input/No protective diode on power supply side.

Timing generator block digital GND.

Timing generator block digital GND. (GND for vertical driver)

CCD vertical register clock output.

Timing generator block digital GND.

Internal SSG enable.
High: Internal SSG valid, Low: External SYNC valid

(With pull-down resistor)

Timing generator block digital power supply.(Power supply for common logic block)

Timing generator block serial interface clock input.
Schmitt trigger input/No protective diode on power supply side.

Vertical sync signal input/output.

Timing generator block test input 1.
Normally fix to GND.

(With pull-down resistor)

CCD vertical register clock output.

Timing generator block 15.0V power supply. (Power supply for vertical driver)

Timing generator block 7.5V power supply. (Power supply for vertical driver)

Timing generator block test input 2.
Normally fix to GND.

(With pull-down resistor)

Timing generator block reset input.
High: Normal operation, Low: Reset control
Normally apply reset during power-on.
Schmitt trigger input/No protective diode on power supply side

Memory write timing pulse output.

Timing generator block serial interface strobe input.
Schmitt trigger input/No protective diode on power supply side

Horizontal sync signal input/output.

Timing generator block digital GND.

CCD vertical register clock output.

CCD electronic shutter pulse output.

Control input used to switch sync system.
High: CKI sync, Low: MCKO sync

(With pull-down resistor)

Vertical direction line identification pulse output.

SSI1

SS4

V1A

V3A

SS1

SSGSL

DD1

SCK1

TEST1

TEST2

RST

WEN

SEN1

SS6

V1B

V3B

SUB

SNCSL

I/O

No.

Symbol

I/O

Description

CXD3406GA

Electrical Characteristics

Timing Generator Block Electrical Characteristics
DC Characteristics

(Within the recommended operating conditions)

DD2

DD3

DD4

DD1

, V

DD5

RST

SSI1, SCK1,
SEN1

TEST1,
TEST2

SNCSL,
SSGSL

VD, HD

H1, H2

XSHP, XSHD,
XRS, PBLK,
CLPOB,
CLPDM,
ADCLK

CKO

MCKO

ID, WEN

V1A, V1B,
V3A, V3B,
V2, V4

SUB

i +

IH1

IL1

IH2

IL2

IH3

IL3

OH1

OL1

OH2

OL2

OH3

OL3

OH5

OL5

OH6

OL6

OH7

OL7

OM1

OM2

OSL

OSH

3.0

0.8V

0.7V

0.8V

d 0.8

b 0.8

a 0.8

d 0.8

10.0

5.0

5.4

3.3

3.6

5.5

3.6

0.2V

0.3V

0.2V

0.4

5.0

7.2

4.0

Feed current where I

= 1.2mA

Pull-in current where I

= 2.4mA

Feed current where I

= 22.0mA

Pull-in current where I

= 14.4mA

Feed current where I

= 3.3mA

Pull-in current where I

= 2.4mA

Feed current where I

= 6.9mA

Pull-in current where I

= 4.8mA

Feed current where I

= 3.3mA

Pull-in current where I

= 2.4mA

Feed current where I

= 2.4mA

Pull-in current where I

= 4.8mA

V1A/B, V2, V3A/B, V4 = 8.25V

V1A/B, V2, V3A/B, V4 = 0.25V

V1A/B, V3A/B = 0.25V

V1A/B, V3A/B = 14.75V

SUB = 8.25V

SUB = 14.75V

Supply voltage 1

Supply voltage 2

Supply voltage 3

Supply voltage 4

Input
voltage 1

Input
voltage 2

Input
voltage 3

Input
voltage 4

Input/output
voltage

Output
voltage 1

Output
voltage 2

Output
voltage 3

Output
voltage 4

Output
voltage 5

Output
voltage 6

Output
current 1

Output
current 2

Item

Pins

Symbol

Conditions

Min.

Typ.

Max.

Unit

This input pin is a schmitt trigger input and it does not have protective diode of the power supply side in the IC.

These input pins are schmitt trigger inputs.

These input pins are with pull-down resistor in the IC.

These input pins are with pull-down resistor in the IC and they do not have protective diode of the power
supply side in the IC.

Note) The above table indicates the condition for 3.3V drive.

OH4

Feed current where I

= 3.3mA

c 0.8

OL4

Pull-in current where I

= 2.4mA

0.4

CXD3406GA

Inverter I/O Characteristics for Oscillation

(Within the recommended operating conditions)

Item

Logical Vth

Input
voltage

Output
voltage

Feedback
resistor

Oscillation
frequency

Pins

OSCI

OSCO

OSCI, OSCO

Symbol

LVth

RFB

Conditions

Feed current where I

= 3.6mA

Pull-in current where I

= 2.4mA

= V

d or V

Min.

0.7V

d 0.8

500k

Typ.

d/2

Max.

0.3V

0.4

Unit

MHz

Item

Logical Vth

Input
voltage

Input
amplitude

Pins

CKI

Symbol

LVth

Conditions

fmax 50MHz sine wave

Min.

0.7V

0.3

Typ.

d/2

Max.

0.3V

Unit

Vp-p

Item

Rise time

Fall time

Output noise voltage

Symbol

TTLM

TTMH

TTLH

TTML

TTHM

TTHL

VCLH

VCLL

VCMH

VCML

Conditions

VL to VM

VM to VH

VL to VH

VM to VL

VH to VM

VH to VL

Min.

200

Typ.

350

Max.

500

1.0

Unit

Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment

(Within the recommended operating conditions)

Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude

is the input amplitude characteristics in the case of input through a capacitor.

Switching Characteristics

(VH = 15.0V, VM = GND, VL = 7.5V)

Notes)
1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for

measures to prevent electrostatic discharge.

2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between

each power supply pin (VH, VL) and GND.

3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.

CXD3406GA

Measurement Circuit

CXD3406GA

SSGSL

DD1

SCK1

TEST1

V1B

V3B

TEST2

RST

WEN

SEN1

V1A

V3A

SUB

SS1

SNCSL

CLPDMI

CLPOBI

ADCLK

XSHPI

XSHDI

PBLKI

DD2

SS3

ADCLKI

DD1

SS1

SS2

SS1

DD1

DD2

CCDIN

SS6

SSI1

MCKO

SS2

DD2

OSCO

OSCI

DD5

SS3

SS5

CKO

CKI

DD3

DD4

XRS

CLPDM

CLPOB

SS4

XSHP

XSHD

PBLK

SCK2

SSI2

TEST3

SS4

SS6

DD5

SEN2

TEST5

DD4

SS3

DD3

TEST4

SS5

Serial interface data

+3.3V

+15.0V

7.5V

CKI

C1 3300pF

C2 560pF

C3 820pF

C4 30pF

C5 215pF

C6 10pF

R1 30

R2 10

CXD3406GA

AC Characteristics

AC characteristics between the serial interface clocks

SSI1

0.2V

0.8V

ts2

th1

ts1

ts3

0.8V

SCK1

SEN1

Symbol

Definition

SSI1 setup time, activated by the rising edge of SCK1

SSI1 hold time, activated by the rising edge of SCK1

SCK1 setup time, activated by the rising edge of SEN1

SEN1 setup time, activated by the rising edge of SCK1

Min.

Typ.

Max.

Unit

Serial interface clock internal loading characteristics (1)

(Within the recommended operating conditions)

th1

Enlarged view

Example: During frame mode

0.2V

ts1

0.2V

V1A

SEN1

0.8V

Symbol

Definition

SEN1 setup time, activated by the falling edge of HD

SEN1 hold time, activated by the falling edge of HD

Min.

Typ.

Max.

102

Unit

µs

Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal period

during which V1A/B and V3A/B values take the ternary value and during that horizontal period.

(Within the recommended operating conditions)

CXD3406GA

Serial interface clock output variation characteristics

Normally, the serial interface data is loaded to the CXD3406GA at the timing shown in "Serial interface clock

internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is

loaded to the CXD3406GA and controlled at the rising edge of SEN1. See "Description of Operation".

0.8V

SEN1

Output signal

tpdPULSE

Symbol

tpdPULSE

Definition

Output signal delay, activated by the rising edge of SEN1

Min.

Typ.

Max.

100

Unit

(Within the recommended operating conditions)

Serial interface clock internal loading characteristics (2)

th1

Enlarged view

0.2V

ts1

0.2V

SEN1

0.8V

Example: During frame mode

Symbol

Definition

SEN1 setup time, activated by the falling edge of VD

SEN1 hold time, activated by the falling edge of VD

Min.

Typ.

Max.

200

Unit

Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD.

(Within the recommended operating conditions)

CXD3406GA

RST

0.2V

tw1

0.8V

VD, HD

MCKO

ts1

th1

0.2V

0.8V

0.2V

RST loading characteristics

Symbol

Definition

RST pulse width

Min.

Typ.

Max.

Unit

(Within the recommended operating conditions)

VD and HD loading characteristics

Symbol

Definition

VD and HD setup time, activated by the rising edge of MCKO

VD and HD hold time, activated by the rising edge of MCKO

Min.

Typ.

Max.

Unit

MCKO load capacitance = 10pF

(Within the recommended operating conditions)

0.8V

MCKO

WEN, ID

tpd1

WEN and ID load capacitance = 10pF

(Within the recommended operating conditions)

Symbol

tpd1

Definition

Time until the above outputs change after the rise of MCKO

Min.

Typ.

Max.

Unit

Output variation characteristics

CXD3406GA

CCD Signal Processor Block Electrical Characteristics

DC Characteristics

(Fc = 18MSPS, DV

DD1

= AV

DD1

= 3.3V, Ta = 25°C)

Item

Supply voltage 1

Supply voltage 2

Supply voltage 3

Analog input
capacitance

Input voltage

A/D clock duty

Output voltage

Pins

DD1

DD2

DD1

DD2

DD3

DD4

DD5

CCDIN

SCK2, SSI2,
SEN2, TEST3,
TEST4, XSHDI,
XSHPI, ADCLKI,
CLPOBI,
CLPDMI, PBLKI

ADCLKI

D0 to D9

Symbol

I +

Conditions

Feed current where I

= 2.0mA

Pull-in current where I

= 2.0mA

Min.

3.0

e 0.9

Typ.

3.3

1.8

1.1

Max.

3.6

0.4

Unit

Analog Characteristics

(Fc = 18MSPS, DV

DD1

= AV

DD1

= 3.3V, Ta = 25°C)

Item

CCDIN input voltage amplitude

PGA maximum gain

PGA minimum gain

ADC resolution

ADC maximum conversion rate

ADC integral non-linearity error

ADC differential non-linearity error

Signal-to-noise ratio

CCDIN input voltage clamp level

CCD optical black signal clamp
level

Symbol

Gmax

Gmin

Fc max

SNR

CLP

Conditions

PGA gain = 0dB, output full scale

PGA gain setting data = "3FFh"

PGA gain setting data = "000h"

PGA gain = 0dB

CCDIN input connected to GND
via a coupling capacitor
PGA gain = 0dB

OBLVL = "8h"
PGA gain = 0dB

Min.

900

Typ.

±1.0

±0.5

1.5

Max.

1100

±5.0

±1.0

Unit

bit

MHz

LSB

SNR = 20 log (full-scale voltage/rms noise)

CXD3406GA

AC Characteristics

AC characteristics between the serial interface clocks

SSI2

0.2V

0.8V

ts2

th1

ts1

ts3

0.8V

SCK2

SEN2

Symbol

Definition

SCK2 clock period

SSI2 setup time, activated by the rise of SCK2

SSI2 hold time, activated by the rise of SCK2

SCK2 setup time, activated by the rise of SEN2

SEN2 setup time, activated by the rise of SCK2

Min.

Typ.

Max.

100

Unit

(Fc = 18MSPS, DV

DD1

= AV

DD1

= 3.3V, Ta = 25°C)

The setting values are reflected to the operation 5 or 6 ADCLKI clocks after the serial data is loaded at the

rise of SEN2.

CXD3406GA

CDS/ADC Timing Chart

N + 1

N 10

CCDIN

XSHPI

XSHDI

ADCLKI

D0 to D9

N 9

N 8

N 7

tw1

N + 2

N + 3

Symbol

Definition

ADCLKI clock period

ADCLKI clock duty

Data latency

Min.

Typ.

Max.

Unit

clocks

(Fc = 18MSPS, DV

DD1

= AV

DD1

= 3.3V, Ta = 25°C)

Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0".

Preblanking Timing Chart

11 Clocks

PBLKI

ADCLKI

D0 to D9

All "0"

CXD3406GA

Description of Operation

Pulses output from the CXD3406GA's timing generator block are controlled mainly by the RST pin and by the

serial interface data. The Pin Status Table is shown below, and the details of serial interface control are

described on page 19 and thereafter.

Pin Status Table

No.

SCK2

SSI2

TEST3

SS4

SS6

DD5

SEN2

TEST5

DD4

DD3

SS3

TEST4

SS5

CCDIN

SS1

DD1

SS1

SS2

DD2

DD1

SS2

SS3

DD2

PBLKI

XSHDI

XSHPI

ADCLKI

CLPOBI

CLPDMI

PBLK

XSHD

XSHP

ADCLK

CLPOB

CLPDM

XRS

DD4

DD3

CKI

ACT

Symbol

No.

Symbol

CAM

SLP

RST

STB

CAM

SLP

RST

STB

CXD3406GA

It is for output. For input, all items are "ACT".

Note) ACT means that the circuit is operating, and DIS means that loading is stopped.

L indicates a low output level, and H a high output level in the controlled status.

Also, VH, VM and VL indicate the voltage levels applied to VH (Pin M5), VM (Pin L4) and VL (Pin M6),

respectively, in the controlled status.

No.

CKO

SS5

SS3

OSCO

MCKO

DD5

DD2

SS2

OSCI

SSI1

SS4

V1A

V3A

SS1

SSGSL

ACT

DIS

ACT

DD1

SCK1

TEST1

TEST2

RST

WEN

SEN1

SS6

V1B

V3B

SUB

SNCSL

ACT

DIS

ACT

DIS

ACT

Symbol

No.

Symbol

CAM

SLP

RST

STB

CAM

SLP

RST

STB

CXD3406GA

Timing Generator Block Serial Interface Control

The CXD3406GA's timing generator block basically loads and reflects the timing generator block serial

interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion

specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value.

Note that some items reflect the timing generator block serial interface data at the falling edge of VD or the

rising edge of SEN1.

SSI1

SCK1

SEN1

There are two categories of timing generator block serial interface data: CXD3406GA timing generator block

drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data").

The details of each data are described below.

CXD3406GA

Control Data

Data

D00

D07

D08

D09

D10

D12

D13

D14

D15

D16

D23

D24

D33

D34

D35

D36

D37

D38

D39

D40

D47

Symbol

CHIP

CTG

MODE

SMD

PTSG

CDAT

LDAD

STB

Function

Chip enable

Category switching

Drive mode switching

Electronic shutter mode switching

Internal SSG output pattern switching

AF drive control data

ADCLK logic phase switching

Standby control

Data = 0

Data = 1

10000001

Enabled

Other values

Disabled

See D08 to D09 CTG.

See D10 to D12 MODE.

See D13 to D14 SMD.

NTSC equivalent

PAL equivalent

See D16 to D23 CDAT.

See D36 to D37 LDAD.

See D38 to D39 STB.

RST

All

CXD3406GA

Shutter Data

Data

D00

D07

D08

D09

D10

D19

D20

D31

D32

D41

D42

D47

Symbol

CHIP

CTG

SVD

SHD

SPL

Function

Chip enable

Category switching

Electronic shutter vertical period
specification

Electronic shutter horizontal period
specification

High-speed shutter position
specification

Data = 0

Data = 1

10000001

Enabled

Other values

Disabled

See D08 to D09 CTG.

See D10 to D19 SVD.

See D20 to D31 SHD.

See D32 to D41 SPL.

RST

All

CXD3406GA

Detailed Description of Each Data

Shared data: D08 to D09 CTG [Category]

Of the data provided to the CXD3406GA by the timing generator block serial interface, the CXD3406GA loads

D10 and subsequent data to each data register as shown in the table below according to the combination of

D08 and D09 .

D09

D08

Description of operation

Loading to control data register

Loading to shutter data register

Test mode

D11

D12

D10

Description of operation

Draft mode (sextuple speed: default)

Frame mode (A field readout)

Frame mode (B Field readout)

Frame mode

AF1 mode

AF2 mode

Note that the CXD3406GA can apply these categories consecutively within the same vertical period. However,

care should be taken as the data is overwritten if the same category is applied.

Control data: D10 to D12 MODE [Drive mode]

The CXD3406GA timing generator block drive mode can be switched as follows. However, the drive mode bits

are loaded to the CXD3406GA and reflected at the falling edge of VD.

Control data: D15 PTSG [Internal SSG output pattern]

The CXD3406GA internal SSG output pattern can be switched as follows. However, the drive mode bits are

loaded to the CXD3406GA and reflected at the falling edge of VD.

D15

Description of operation

NTSC equivalent pattern

PAL equivalent pattern

The VD period in each pattern is defined as follows for each drive mode.

Only 944H and 945H are 1208ck period.

See the Timing Charts for the actual operation.

NTSC equivalent pattern

PAL equivalent pattern

Frame mode

918H + 1716ck

945H

Draft mode

262H + 1144ck

314H + 1568ck

AF1 mode

131H + 572ck

157H + 784ck

AF2 mode

65H + 1430ck

78H + 1536ck

CXD3406GA

Control data: D36 to D37 LDAD [ADCLK logic phase]

This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO.

Control data: D38 to D39 STB [Standby]

The operating mode of the timing generator block is switched as follows. However, the standby bits are loaded

to the CXD3406GA and control is applied immediately at the rising edge of SEN1.

D37

D36

Degree of adjustment (°)

180

270

D39

D38

Symbol

CAM

SLP

STB

Operating mode

Normal operating mode

Sleep mode

Standby mode

See the Pin Status Table for the pin status in each mode.

CXD3406GA

The frame shift data is expressed as shown in the table below using D16 to D23 CDAT.

MSB

LSB

D23

D22

D21

D20

D19

D18

D17

D16

CDAT is expressed as 69h .

Its definition area is specified as follows.

AF1 mode: 00h

CDAT

FFh (11 to 23H)

AF2 mode: 00h

CDAT

FFh (14 to 27H)

Control data: [AF drive]

The CXD3406GA controls the drive of the vertical cut-out area of the line in AF1/AF2 mode by using control

data D16 to D23 CDAT. This mode has a function on purpose to raise frame rate for auto focus (AF), and

cannot support operation such as electrical image stabilization.

The AF drive bits are loaded to the CXD3406GA and reflected at the falling edge of VD. As shown in the figure

below, first, the fixed stage is swept at high speed, and it goes to readout period and vertical OB period. Then

normal transfer is performed equivalent to draft mode from the frame shift to the stage specified by the serial

interface data to the timing of the falling edge of the next VD.

Therefore, the number of frame shift stages applied to CDAT and the control by VD period are conditions for

its application.

V1A

Vck

MODE

00h

FFh

CDAT

00h

Frame shift

Normal transfer

High-speed sweep

The number of high-speed sweep are different according to the selected mode. They are specified as follows.

AF1 mode: 138 stages (0 to 7H)

AF2 mode: 208 stages (0 to 11H)

CXD3406GA

Control data/shutter data: [Electronic shutter]

The CXD3406GA realizes various electronic shutter functions by using control data D13 to D14 SMD and

shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL.

These functions are described in detail below.

First, the various modes are shown below.

These modes are switched using control data D13 to D14 SMD.

D14

D13

Description of operation

Electronic shutter stopped mode

High-speed/low-speed shutter mode

HTSG control mode

The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example.

However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC.

MSB

LSB

D29

D28

D31

D30

D27

D26

D25

D24

D23

D22

D21

D20

SHD is expressed as 1C3h .

[Electronic shutter stopped mode]

During this mode, all shutter data items are invalid.

SUB is not output in this mode, so the shutter speed is the accumulation time for one field.

[High-speed/low-speed shutter mode]

During this mode, the shutter data items have the following meanings.

The period during which SVD and SHD are specified together is the shutter speed. Concretely, when

specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed shutter, or in other

words when SVD is set to "001h" or higher, the serial interface data is not loaded until this period is finished.

The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of

horizontal periods applied to SHD can be considered as (number of SUB pulses 1). However, in the frame

mode A field, it matches (number of SUB pulses + 1). This is a specification for flickerless when the same

mode is repeated. But this change may not occur because of flickerless depending on the conditions during

low-speed shutter.

Note) The bit data definition area is assured in terms of the CXD3406GA functions, and does not assure the

CCD characteristics.

Symbol

SVD

SHD

SPL

Data

D10 to D19

D20 to D31

D32 to D41

Description

Number of vertical periods specification (000h

SVD

3FFh)

Number of horizontal periods specification (000h

SHD

7FFh)

Vertical period specification for high-speed shutter operation (000h

SPL

3FFh)

CXD3406GA

SHD

V1A

SUB

WEN

SMD

000h

002h

SVD

050h

10Fh

SHD

SVD

SPL

SHD

V1A

SUB

WEN

SMD

000h

001h

SPL

000h

002h

SVD

0A3h

10Fh

SHD

SVD

Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the

low-speed shutter period.

In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.

Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD.

Using this function, it is possible to achieve smooth exposure time transitions when changing from low-speed

shutter to high-speed shutter or vice-versa.

CXD3406GA

SUB

CLPOB

CLPDM

V1A

High-speed sweep block

V1B

V3A

V3B

CCD OUT

1547

1549

1542

1544

1546

1548

1550

1539

1541

1543

1545

3
1

24682

13579

PBLK

WEN

Field

B Field

918

810

The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in e

ach horizontal period.

ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.

VD of this chart is NTSC equivalent pattern (918H + 1716ck units). For PAL equivalent pattern, it is 945H units, but 1208ck per

iod only for 944H and 945H.

Chart-1 Vertical Direction Timing Chart

MODE

Frame mode

Applicable CCD image sensor

·
ICX252/262

CXD3406GA

SUB

V1A

V3A

V3B

CLPOB

CLPDM

PBLK

V1B

CCD OUT

15
10
3

13
8
1

546

539

534

527

544

537

532

525

549

10
3

8
1

546

539

534

527

544

537

532

525

549

WEN

262

261

262

261

The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in e

ach horizontal period.

ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.

VD of this chart is NTSC equivalent pattern (262H + 1144ck units). For PAL equivalent pattern, it is 314H + 1568ck units.

Chart-2 Vertical Direction Timing Chart

MODE

Draft mode

Applicable CCD image sensor

·
ICX252/262

CXD3406GA

CCD OUT

WEN

CLPOB

CLPDM

PBLK

V1A

V1B

V3B

SUB

V3A

131

High-speed

sweep block

High-speed

sweep block

Frame shift block

The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in e

ach horizontal period.

ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.

138 stages are fixed for high-speed sweep block ; 0 to 255 stages can be specified by the serial interface for the frame shift

block.

VD of this chart is NTSC equivalent pattern (131H + 572ck units). For PAL equivalent pattern, it is 157H + 784ck units.

Chart-3 Vertical Direction Timing Chart

MODE

AF1 mode

Applicable CCD image sensor

·
ICX252/262

CXD3406GA

CCD OUT

WEN

CLPOB

CLPDM

PBLK

V1A

V1B

V3B

SUB

V3A

High-speed sweep block

Frame shift block

High-speed sweep block

Frame shift block

The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in e

ach horizontal period.

ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.

208 stages are fixed for high-speed sweep block ; 0 to 255 stages can be specified by the serial interface for the frame shift

block.

VD of this chart is NTSC equivalent pattern (65H + 1430ck units). For PAL equivalent pattern, it is 78H + 1536ck units.

Chart-4 Vertical Direction Timing Chart

MODE

AF2 mode

Applicable CCD image sensor

·
ICX252/262

CXD3406GA

148

MCKO

V1A/B

V3A/B

SUB

PBLK

CLPOB

CLPDM

(2288)

100

150

174

200

250

WEN

198

172

198

157

128

138

HD of this chart indicates the actual CXD3406GA load timing.

The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.

The HD fall period should be between approximately 2.9 to 9.5µ

(when the drive frequency is 18MHz). This chart shows a period

of 115ck (6.4µ

s). Internal SSG is at this timing.

SUB is output at this timing shown above when output is controlled by the serial interface data.

ID and WEN are output at this timing shown above at the position shown in Chart-1.

Chart-5 Horizontal Direction Timing Chart

MODE

Frame mode

Applicable CCD image sensor

·
ICX252/262

CXD3406GA

MCKO

V1A/B

V3A/B

SUB

PBLK

CLPOB

CLPDM

(2288)

100

150

106

174

200

250

WEN

198

172

198

120

140

102

151

111

156

129

142

138

124

133

HD of this chart indicates the actual CXD3406GA load timing.

The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.

The HD fall period should be between approximately 2.9 to 9.5µ

(when the drive frequency is 18MHz). This chart shows a period

of 115ck (6.4µ

s). Internal SSG is at this timing.

SUB is output at this timing shown above when output is controlled by the serial interface data.

ID and WEN are output at this timing shown above at the position shown in Charts-2, 3 and 4.

Chart-6 Horizontal Direction Timing Chart

MODE

Draft/AF1/AF2 mode

Applicable CCD image sensor

·
ICX252/262

CXD3406GA

MCKO

V1A/B

V3A/B

SUB

PBLK

CLPOB

CLPDM

(2288)

100

150

139

197

200

250

WEN

172

100

129

138

100

129

168

187

274

158

168

226

158

139

255

274

245

216

187

216

245

197

255

226

HD of this chart indicates the actual CXD3406GA load timing.

The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.

The HD fall period should be between approximately 2.9 to 9.5µ

(when the drive frequency is 18MHz). This chart shows a period

of 115ck (6.4µ

s). Internal SSG is at this timing.

SUB is output at this timing shown above when output is controlled by the serial interface data.

High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 26H of 768ck(#1038).

Chart-7 Horizontal Direction Timing Chart

(High-speed sweep: C)

MODE

Frame mode

Applicable CCD image sensor

·
ICX252/262

CXD3406GA

MCKO

V1A/B

V3A/B

SUB

PBLK

CLPOB

CLPDM

(2288)

100

150

109

147

200

250

WEN

172

121

140

105

140

128

102

140

159

197

254

109

147

166

102

159

178

216

223

261

280

273

128

204

242

121

235

273

261

216

223

178

185

166

185

204

242

197

235

254

219

HD of this chart indicates the actual CXD3406GA load timing.

The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.

The HD fall period should be between approximately 2.9 to 9.5µ

(when the drive frequency is 18MHz). This chart shows a period

of 115ck (6.4µ

s). Internal SSG is at this timing.

SUB is output at this timing shown above when output is controlled by the serial interface data.

WEN is output at this timing shown above at the position shown in Chart-3 and 4.

High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 6H of 2056ck (#138) in AF1 mode and 10H of 884ck (#208) in AF2

mode.

Frame shift of V1A/B, V2, V3A/B and V4 receives the output control by the serial interface data and can specify up to #255 for

both of AF1/AF2 mode.

ID is output at the timing shown with dotted line during frame shift.

Chart-8 Horizontal Direction Timing Chart

(High-speed sweep: F)

(Frame shift: G)

MODE

AF1/AF2 mode

Applicable CCD image sensor

·
ICX252/262

CXD3406GA

Field]

[B Field]

[A]

[B]

V3B

V1A

V1B

V3A

V1A

V1B

V3A

(2288)

110

128

148

157

181

211

241

(2288)

128

148

110

157

1100

1130

1160

1190

1280

1310

1250

Logic alignment portion

HD of this chart indicates the actual CXD3406GA load timing.

The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.

The HD fall period should be between approximately 2.9 to 9.5µ

(when the drive frequency is 18MHz). This chart shows a period

of 115ck (6.4µ

s). Internal SSG is at this

timing.

Chart-9 Horizontal Direction Timing Chart

MODE

Frame mode

Applicable CCD image sensor

·
ICX252/262

CXD3406GA

102

106

111

115

120

124

129

133

138

142

147

151

156

102

106

111

115

120

124

129

133

138

142

147

151

156

[D]

V3B

V1A

V1B

V3A

(2288)

1130

1160

1190

1010

1040

1070

1100

1220

1250

1280

1310

1340

1370

1400

1430

HD of this chart indicates the actual CXD3406GA load timing.

The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.

The HD fall period should be between approximately 2.9 to 9.5µ

(when the drive frequency is 18MHz). This chart shows a period

of 115ck (6.4µ

s). Internal SSG is at this timing.

Chart-10 Horizontal Direction Timing Chart

MODE

Draft/AF1/AF2 mode

Applicable CCD image sensor

·
ICX252/262

CXD3406GA

Chart-12 Vertical Direction Sequence Chart

MODE

Draft

Frame

Draft

Applicable CCD image sensor

·
ICX252/262

V1A

V1B

V3A

V3B

SUB

Mechanical shutter

Exposure time

CCD OUT

MODE

SMD

SHD

Open

000

050h

000h

050h

This chart is a driving timing chart example of electronic shutter normal operation.

Data exposed at D includes blooming component. For details, see the CCD image sensor Data Sheet.

The CXD3406GA does not generate the pulse to control mechanical shutter operation.

The switching timing of the drive mode and the electronic shutter data is not the same.

CXD3406GA

CCD Signal Processor Block Serial Interface Control

The CXD3406GA's CCD signal processor block basically loads the CCD signal processor block serial interface
data sent in the following format at the rising edge of SEN2, and the setting values are then reflected to the
operation 6 ADCLKI clocks after that.
CCD signal processor block serial interface control requires clock input to ADCLKI in order to load and reflect
the serial interface data to operation, so this should normally be performed when the timing generator block is
in the normal operation mode.

SSI2

SCK2

SEN2

There are four categories of CCD signal processor block serial interface data: standby control data, PGA gain
setting data, OB clamp level setting data, and input pulse polarity setting data.
Note that when data from multiple categories is loaded consecutively, the data for the category loaded last is
valid and data from other categories is lost. When transferring data from multiple categories, raise SEN2 for
each category and wait until the setting value 6 ADCKLI clocks after that has been reflected to operation, then
transmit the next category.
The detail of each data are described below.

Standby Control Data

Data

D00

D01

D03

D04

D14

D15

Symbol

TEST

CTG

FIXED

STB

Function

Test code

Category switching

Standby control

Data = 0

Data = 1

Set to 0.

D01 to D03 CTG

Set to All 0.

Normal operating mode

Standby mode

Data

D00

D01

D03

D04

D05

D06

D15

Symbol

TEST

CTG

FIXED

GAIN

Function

Test code

Category switching

PGA gain setting data

Data = 0

Data = 1

Set to 0.

D01 to D03 CTG

Set to All 0.

See D06 to D15 GAIN.

PGA Gain Setting Data

CXD3406GA

Data

D00

D01

D03

D04

D11

D12

D15

Symbol

TEST

CTG

FIXED

OBLVL

Function

Test code

Category switching

OB clamp level setting data

Data = 0

Data = 1

Set to 0.

D01 to D03 CTG

Set to All 0.

See D12 to D15 OBLVL.

OB Clamp Level Setting Data

Data

D00

D01

D03

D04

D12

D13

D15

Symbol

TEST

CTG

FIXED

POL

Function

Test code

Category switching

Input pulse polarity setting data

Data = 0

Data = 1

Set to 0.

D01 to D03 CTG

Set to All 0.

Input Pulse Polarity Setting Data

CXD3406GA

Detailed Description of Each Data

Shared data: D01 to D03 CTG [Category]

Of the data provided to the CXD3406GA by the CCD signal processor block serial interface, the CXD3406GA

loads D04 and subsequent data to each data register as shown in the table below according to the combination

of D01 to D03 .

PGA gain setting data: D06 to D15 GAIN [PGA gain]

The CXD3406GA can set the programmable gain amplifier (PGA) gain from 6dB to +42dB in 1024 steps by

using PGA gain setting data D06 to D15 GAIN.

The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN.

D01

D02

D03

Description of operation

Loading to standby control data register

Loading to PGA gain setting data register

Loading to OB clamp level setting data register

Loading to input pulse polarity setting data register

Access prohibited

Standby control data: D15 STB [Standby]

The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor

block is in standby mode, only the serial interface is valid.

D15

Description of operation

Normal operating mode

Standby mode

MSB

LSB

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

GAIN is expressed as 1C3h .

For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting

values are 6dB, 0dB, +20dB, +34dB and +42dB.

CXD3406GA

OB clamp level setting data: D12 to D15 OBLVL [OB clamp level]

The CXD3406GA can set the OPB clamp output value from 0 to 60LSB in 4LSB steps by using CCD signal

processor block control data D12 to D15 OBLVL.

The OPB clamp output setting data is expressed as shown in the table below using D12 to D15 OBLVL.

MSB

LSB

D12

D13

D14

D15

OBLVL is expressed as 6h .

For example, when OBLVL is set to "0h", "1h", "8h" and "Fh", the respective OPB clamp output setting values

are 0LSB, 4LSB, 32LSB and 60LSB.

CXD3406GA

Application Circuit Block Diagram

SEN2

SCK2

SSI2

CCD

ICX252/262

TG/CDS/PGA/ADC

CXD3406GA

Controller

SSI1

SEN1

SCK1

TEST5

TEST4

TEST3

TEST2

TEST1

OSCO

CKI

OSCI

D0 (LSB)

Signal

Processor

Bloc

D9 (MSB)

MCK

SSGSL

SNCSL

RST

WEN

0.1µF

XSHPI

XSHDI

PBLKI

CLPDMI

CLPOBI

XSHP

XSHD

PBLK

CLPDM

CLPOB

ADCLK

ADCLKI

0.1µF

1µF

CCDIN

CCDOUT

390pF

240pF

V1A

V1B

V3A

V3B

SUB

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility fo

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same

This block diagram illustrates connections with each circuit

block, and is not an actual circuit diagram. See the CCD

image sensor data sheet for an example of specific circuit

connections with the CCD image sensor.

CXD3406GA

Notes on Operation

1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the

figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In

addition, start up the timing generator block V

DD1

, V

DD2

, V

DD3

, V

DD4

and V

DD5

pin and CCD signal processor

block DV

DD1

, DV

DD2

, AV

DD1

, AV

DD2

, AV

DD3

, AV

DD4

and AV

DD5

pin power supplies at the same time either

before or at the same time as the VH pin power supply is started up.

2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator

block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by

initializing the serial data.

3. Separate the timing generator block V

DD1

, V

DD2

, V

DD3

, V

DD4

and V

DD5

pins from the CCD signal processor

block DV

DD1

, DV

DD2

, AV

DD1

, AV

DD2

, AV

DD3

, AV

DD4

and AV

DD5

pins.

Also, the ADC output driver stage is connected to the dedicated power supply pin DV

DD1

. Separating this

pin from other power supplies is recommended to avoid affecting the internal analog circuits.

4. The difference in potential between the timing generator block V

DD4

pin supply voltage 3 V

c and the CCD

signal processor block DV

DD1

, DV

DD2

, AV

DD1

, AV

DD2

, AV

DD3

, AV

DD4

and AV

DD5

pin supply voltages 1 V

2 V

f and 3 V

g should be 0.1V or less.

5. The timing generator block and CCD signal processor block ground pins should use a shared ground which

is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the

timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to

the analog ground. The difference in potential between the timing generator block V

SS1

, V

SS2

, V

SS3

, V

SS4

SS5

, V

SS6

and VM and the CCD signal processor block DV

SS1

, DV

SS2

, DV

SS3

, AV

SS1

, AV

SS2

, AV

SS3

, AV

SS4

SS5

and AV

SS6

should be 0.1V or less.

6. Do not perform serial communication with the CCD signal processor block during the effective image

period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which

are used by the CCD signal processor block, use of the dedicated ports is recommended. When using

these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the

effects on picture quality before use.

15.0V

7.5V

20%

CXD3406GA

Package Outline

Unit: mm

96PIN LFLGA

PACKAGE MASS

PACKAGE STRUCTURE

ORGANIC SUBSTRATE

0.3 g

PACKAGE MATERIAL

TERMINAL TREATMENT

TERMINAL MATERIAL

GOLD PLATING

NICKEL PLATING

SONY CODE

EIAJ CODE

JEDEC CODE

LFLGA-96P-02

P-LFLGA96-12X8-0.8

1.3 MAX

0.10

DETAIL X

0.2

PIN 1 INDEX

0.2

12.0

8.0

0.2

0.15

0.8

1 2 3 4 5 6 7 8 9

0.8

S A B

96 -

0.45 ± 0.05

0.5

0.50

0.5

0.9

1.2

0.8

0.10MAX

0.5

0.08

(0.3)

Sony Corporation

96PIN LFLGA

PACKAGE MASS

PACKAGE STRUCTURE

ORGANIC SUBSTRATE

0.3g

PACKAGE MATERIAL

TERMINAL TREATMENT

TERMINAL MATERIAL

SONY CODE

EIAJ CODE

JEDEC CODE

LFLGA-96P-051

P-LFLGA96-12.0X8.0-0.8

1.3 MAX

0.10

DETAIL X

0.2

PIN 1 INDEX

0.2

12.0

8.0

0.2

0.15

0.8

1 2 3 4 5 6 7 8 9

0.8

S A B

96 -

0.45

0.05

0.5

0.50

0.5

0.9

1.2

0.8

0.10MAX

0.5

0.08

(0.3)

NICKEL & GOLD PLATING

COPPER

Oita Ass'y

HITACHI TOKYO Ass'y

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